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Introduction to JTAG Surface-mount technology rang the death knell for bed-of-nails testing. That's why a consortium of companies called the Joint Test Access Group came together to define a standard for boundary-scan testing of ICs and boards. Here's a primer on the technology. One disadvantage of shrinking technology is that the testing of small devices gets exponentially more complex. When circuit boards were large, we tested them with techniques such as bed-of-nails, which employed small spring-loaded test probes to make connections with solder pads on the bottom of the board. Such test fixtures were custom made, expensive, and inefficient, and much of the testing could not be performed until the design was complete. The problems with bed-of-nails testing were exacerbated as board dimensions got smaller and surface-mount packaging technology improved. If devices were mounted on both sides of a circuit board, no attachment points were left for the test equipment. Boundary scan To find a solution to these problems, a group of European electronics companies formed a consortium in 1985 called the Joint Test Action Group (JTAG). The consortium devised a specification for performing boundary-scan hardware testing at the IC level. In 1990, that specification resulted in IEEE 1149.1, a standard that established the details of access to any chip with a so-called JTAG port. The specification JTAG devised uses boundary-scan technology, which enables engineers to perform extensive debugging and diagnostics on a system through a small number of dedicated test pins. Signals are scanned into and out of the I/O cells of a device serially to control its inputs and test the outputs under various conditions. Today, boundary-scan technology is probably the most popular and widely used design-for-test technique in the industry. Test pins Devices communicate to the world via a set of I/O pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These registers are connected in a dedicated path around the device's boundary (hence the name), as shown in Figure 1. The path creates a virtual access capability that circumvents the normal inputs and provides direct control of the device and detailed visibility at its outputs. [upload=gif]uploadImages/20021171039827515.gif[/upload] Figure 1: An integrated circuit with boundary scan During testing, I/O signals enter and leave the chip through the boundary-scan cells. The boundary-scan cells can be configured to support external testing for interconnection between chips or internal testing for logic within the chip. To provide the boundary scan capability, IC vendors add additional logic to each of their devices, including scan registers for each of the signal pins, a dedicated scan path connecting these registers, four or five additional pins, and control circuitry. The overhead for this additional logic is minimal and generally well worth the price to have efficient testing at the board level. Test Access Port The boundary-scan control signals, collectively referred to as the Test Access Port (TAP), define a serial protocol for scan-based devices. There are five pins: TCK/clock synchronizes the internal state machine operations. TMS/mode select is sampled at the rising edge of TCK to determine the next state. TDI/data in is sampled at the rising edge of TCK and shifted into the device's test or programming logic when the internal state machine is in the correct state. TDO/data out represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state. TRST/reset (optional), when driven low, resets the internal state machine. The TCK, TMS, and TRST input pins drive a 16-state TAP controller state machine. The TAP controller manages the exchange of data and instructions. The controller advances to the next state based on the value of the TMS signal at each rising edge of TCK. With the proper wiring, you can test multiple ICs or boards simultaneously. An external file, known as a Boundary-Scan Description Language (BSDL) file, defines the capabilities of any single device's boundary-scan logic. Test process The standard test process for verifying a device or circuit board using boundary-scan technology is as follows: The tester applies test or diagnostic data on the input pins of the device. The boundary-scan cells capture the data in the boundary scan registers monitoring the input pins. Data is scanned out of the device via the TDO pin, for verification. Data can then be scanned into the device via the TDI pin. The tester can then verify data on the output pins of the device. Simple tests can find manufacturing defects such as unconnected pins, a missing device, an incorrect or rotated device on a circuit board, and even a failed or dead device. The primary advantage of boundary-scan technology is the ability to observe data at the device inputs and control the data at the outputs independently of the application logic. Another benefit is the ability to reduce the number of overall test points required for device access. With boundary scan there are no physical test points. This can help lower board fabrication costs and increase package density. Boundary scan provides a better set of diagnostics than other test techniques. Conventional techniques apply test vectors (patterns) to the inputs of the device and monitor the outputs. If there is a problem with the test, it can be time consuming to isolate the problem. Additional tests have to be run to isolate the failure. With boundary scan, the boundary-scan cells observe device responses by monitoring the input pins of the device. This enables easy isolation of various classes of test failures, such as a pin not making contact with the circuit board. Boundary scan can be used for functional testing and debugging at various levels, from internal IC tests to board-level tests. The technology is even useful for hardware/software integration testing. Debug Some test equipment and ASIC-cell companies have defined proprietary extensions that use the JTAG capability to implement software debug functions. With the proper support built into a target CPU, you can use this interface to download code, execute it, and examine register and memory values. These functions cover the majority of the low-level functionality of a typical debugger. An inexpensive remote debugger can be run on a workstation or PC to assist with software debug. Boundary-scan technology is also used for emulation. The emulator front-end acts as the scan manager by controlling the delivery of scan information to and from the target and the debugger window. (Of course, when a host controls the JTAG scan information, it needs to know if other devices are connected in the scan chain.) JTAG also allows the internal components of the device (the CPU, for example) to be scanned. This means you can use JTAG to debug embedded devices by allowing access to any part of the device that is accessible via the CPU, and still test at full speed. This has since become a standard emulation debug method used by silicon vendors. JTAG can also provide system level debug capability. Having extra pins on a device provides additional system integration capabilities for benchmarking, profiling, and system level breakpoints. As an engineering manager at Texas Instruments, Rob Oshana manages DSP and ARM code generation and build technologies, as well as DSP emulation technology. Contact him at roshana@ti.com.

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